Have you ever heard of OZAI?It is a blind box product of Heyone,which was first launched in May 2022.In June this year,the two-year-old OZAI launched a new model featuring the theme“Spring Garden Party”,which was snapped up instantly.A netizen who participated in the snapping-up of these during the official live broadcast posted that there were 20,000 people online at that time,and the link showed“sold out”only one second after it went online.Offline sales were even more popular.Two days before the sale,consumers lined up at the TOPTOY store.How does a blind box with unknown contents become a best seller?
S-boxes play a central role in the design of symmetric cipher schemes.For stream cipher appli-cations,an s-box should satisfy several criteria such as high nonlinearity,balanceness,correlation immunity,and so on.In this paper,by using disjoint linear codes,a class of s-boxes possessing high nonlinearity and 1st-order correlation immunity is given.It is shown that the constructed correlation immune S-boxes can possess currently best known nonlinearity,which is confirmed by the example 1st-order correlation immune(12,3)s-box with nonlinearity 2000.In addition,two other frameworks concerning the criteria of balanced and resiliency are obtained respectively.
The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.
