随着集成电路工艺的发展,众核处理器体系结构逐渐成为计算机体系结构设计者的研究热点。众核体系结构通过任务级的并行来提升整个处理器的性能。然而,指令级的并行性仍然是众核设计者需要认真考虑的问题。对浮点运算效率和加速比进行了形式化描述,验证了进行指令级调度的必要性。对处理器核内流水线进行详细分析,指出了指令级调度的一般性问题。提出了在众核结构上使用指令级调度和软件流水的方法。针对Splash2程序集里的LU分解算法,使用众核结构的硬件支持,在Scratched Pad Memory(SPM)上给出了调度指令的方案。在众核仿真器Godson-T上仿真了经过指令级调度后的算法,当使用64个线程处理512×512的矩阵时,程序性能达到调度前性能的4倍。
A low-power voltage-mode-logic （VML） transmitter fabricated in TSMC 28 nm CMOS technology is presented. The VML driver outputs a high-swing signal and consumes less power than a current-mode-logic （CML） driver. To further reduce power, the driver is divided into two voltage domains by level shifters. Moreover, the proposed driver topology can achieve mutually decoupled impedance self-calibration and equalization control. The measurement result shows that the transmitter merely dissipates 23 roW/channel while exhibiting an 880 mV differential eye height at 4.488 Gb/s.
