调频范围是压控振荡器的一个重要的性能指标,当调频范围增大时,振荡器的振幅会随着频率的不同而改变。为了保证压控振荡器在调频范围内振幅恒定,提出了一种新型的自动振幅控制的电路结构。自动振幅控制电路由峰值检测、比较器和低通滤波器几部分构成,自动振幅控制电路与压控振荡器组成的反馈环路控制压控振荡器的输出恒定。电路采用标准的0.35μm CM O S工艺流片并进行测试。测试结果表明:压控振荡器的调频范围为18.2MH z^24.3MH z,达到了28.7%,自动振幅控制电路保证压控振荡器的振幅变化仅为8.7%。
An automatic IQ phase calibration method implemented in a 2.4GHz direct conversion receiver is proposed. It uses a delay locked loop （DLL） with a proposed quadrature phase detector to greatly reduce the phase error. The receiver is fabricated in a 0.18μm CMOS process. Measurements show that the IQ phase error can be calibrated within 1°,which satisfies the system requirement.
We report a low power ASK IF receiver for short-range wireless systems,which includes an AGC loop that compensates the channel attenuation and an ASK detector. A novel current-limited transconductor and feed-forward differential peak detector have been designed to maintain a high compression ratio and fast response for the AGC with lower power consumption. A storage unit with a zero and a feed-forward structure have been introduced into the peak detector to control the damping characteristic of the AGC loop. A rectifier and low-pass filter included in the ASK detector have been integrated into a more compact structure to further lower the power consumption. The simulation results show the feasibility of the proposed technique.
A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying （GMSK）modulation is presented. A pre-compensation fractional-N phase-locked loop（PLL）is adopted in the modulator.The transfer function of the type- Ⅱ third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out. Methods to calibrate the important loop parameters arc introduced. A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design. The designed circuits are simulated in a 0.18gm 1P6M CMOS process. The power consumption of the PLL is only about llmW with the low power consideration in building blocks design, and the data rate of the modulator can reach 2Mb/s.
