为缓解负偏置温度不稳定性(negative bias temperature instability,NBTI)效应引起的电路老化,提高电路可靠性,提出一种在电路待机状态下应用输入向量约束的门替换方法.运用动态和静态的NBTI模型进行感知NBTI的静态时序分析,确定潜在关键路径,考虑路径相关性的关键门算法以确定关键门,并生成能使关键门最大限度处于恢复阶段的输入向量.对输入向量无法控制的关键门采用门替换方法进行内部控制.对ISCAS标准电路的实验结果表明,电路时序余量为5%时,该方法的平均门替换率降低到9.68%,时延改善率提高到39.65%.
NBTI-induced transistor aging has become a prominent factor affecting the reliability of circuits. Reducing leakage consumption is one of the major design goals. Domino logic circuits are applied extensively in high-performance integrated circuits. A circuit technique for mitigating NBTI-induced degradation and reduce standby leakage current is presented in this paper. Two transistors are added to the standard domino circuit to pull both the dynamic node and the output up to VDo, which puts both the keeper and the inverter pMOS transistor into recovery mode in standby mode. Due to the stack effect, leakage current is reduced by the all-0 input vector and the added transistors. Experimental results reveal up to 33% NBTI-induced degradation reduction and up to 79% leakage current reduction.
随着集成电路工艺进入微纳尺度,组合逻辑电路的软错误率不断增加,电路的可靠性受到严重威胁。传统的逻辑门加固结构通常会带来较大的面积开销。文章采用具有鲁棒容错性能的级联电压开关逻辑(cascade voltage switch logic,简称CVSL)门单元,提出"CVSL门对"结构对电路输出端进行选择性加固,以较小面积开销实现电路容错性能的大幅提升。Hspice仿真实验表明"CVSL门对"结构具有良好的容忍故障脉冲性能。ISCAS-89基准电路实验结果表明,被加固电路软错误防护率达90%以上,仅带来12.54%的面积开销,比CWSP单元加固法节省46.57%,比三模冗余结构加固法节省91.78%。
