Most existing system-on-chip (SoC) architectures are for microprocessor-centric designs. They are not suitable for computing intensive SoCs, which have their own configurability, extendibility, performance, and data exchange characteristics. This paper analyzes these characteristics and gives design principles for computing intensive SoCs. Three architectures suitable for different situations are compared with selection criteria given. The architectural design of a high performance network security accelerator (HPNSA) is used to elaborate on the design techniques to fully exploit the performance potential of the architectures. A behavior-level simulation system is implemented with the C++ programming language to evaluate the HPNSA performance and to obtain the optimum system design parameters. Simulations show that this architecture provides high performance data transfer.
We analyze the drawbacks of generally distributed time transition stochastic Petri nets(GDTT_SPN) in evaluating the performance of parallel systems,and propose a more general model,stochastic individual predicate/transition nets(SIPTN). SIPTN has higher modeling power and could provide more realistic models compared to GDTT_SPN,because in SIPTN the sojourn time distribution is determined not only by the transition,but also by the individuals. It is further proved that GDTT_SPN is a subset of SIPTN. As SIPTN introduces folding techniques from predicate/transition nets,SIPTN models have simpler and more intuitive graphic notations and accordingly higher usability,and thus are suitable for constructing simulation models for parallel systems.
Yao YUE Chun-ming ZHANG Hai-xin WANG Guo-qiang BAI Hong-yi CHEN
