An integrated circuit design of a high speed multiplier for direct sigma–delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier's stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18- m CMOS process. The test results demonstrate thatthechiprealizesthemultiplicationfunctionandexhibitsanexcellentperformance.Itcanworkat4GHzandthe voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard.Additionally, the analysis of the multiplier's noise performance is also presented.
The conventional circuit model of a bit-stream adder based on sigma delta(∑Δ) modulation is improved with pipeline technology to make it work correctly at high frequencies.The integrated circuit(IC) of the bit-stream adder is designed with the source coupled logic structure and designed at the transistor level to increase the operating frequency.The IC is fabricated in TSMC's 0.18-μm CMOS process.The chip area is 475×570μm^2.A fully digital∑Δsignal generator is designed with a field programmable gate array to test the chip.Experimental results show that the chip meets the function and performance demand of the design,and the chip can work at a frequency of higher than 4 GHz.The noise performance of the adder is analyzed and compared with both theory and experimental results.
