Two layout and process key parameters for improving high voltage nLEDMOS （n-type lateral extended drain MOS） transistor hot carrier performance have been identified. Increasing the space between Hv-pwell and n-drift region and reducing the n-drift implant dose can dramatically reduce the device hot carder degradations, for the maximum impact ionization rate near the Bird Beak decreases or its location moves away from the Si/SiO2 interface. This conclusion has been analyzed in detail by using the MEDICI simulator and it is also confirmed by the test results.
研究了常规LEDM O S,带有两块多晶硅场极板LEDM O S以及带有两块多晶硅场极板和一块铝场极板的LEDM O S表面电场分布情况,重点研究了多块场极板在不同的外加电压下,三种LEDM O S的表面峰值电场和导通电阻的变化情况。模拟结果和流水实验结果都表明:多块场极板是提高LEDM O S击穿电压的一种有效方法,而且场极板对导通电阻的影响很小。研究结果还表明:由于金属铝引线下面的氧化层很厚,所以铝引线几乎不会影响到LEDM O S的击穿特性。
A SPICE sub-circuit model is developed for high-voltage LDMOS transistors integrated in PDP driver ICs. The model accounts for intrinsic LDMOS phenomena such as the quasi-saturation effects, voltage-dependent drift resistance, self-heating effects, and Miller capacitance. In contrast to most physical or sub-circuit models, the proposed model not only provides precise simulated results,but also brings a very fast modeling procedure. Furthermore,the model also can be embedded in a commercial SPICE simulator easily. The simulation results using the presented models agree well with the measured ones and the error is less than 5%.
The on-resistance degradations of the p-type lateral extended drain MOS transistor （pLEDMOS） with thick gate oxide under different hot carrier stress conditions are different, which has been experimentally investigated. This difference results from the interface trap generation and the hot electron injection, and trapping into the thick gate oxide and field oxide of the pLEDMOS transistor. An improved method to reduce the on-resistance degradations is also presented, which uses the field oxide as the gate oxide instead of the thick gate oxide. The effects are analyzed with a MEDICI simulator.
The failure experiments of the P-LDMOS （lateral double diffused metal oxide semiconductor） demonstrate that the high peak electrical fields in the channel region of high-voltage P-LDMOS will reinforce the hot-carrier effect, which can greatly reduce the reliability of the P-LDMOS. The electrical field distribution and two field peaks along the channel surface are proposed by Tsuprem-4 and Medici. The reason of resulting in the two electrical field peaks is also discussed. Two ways of reducing the two field peaks, which are to increase the channel length and to reduce the channel concentration, are also presented. The experimental results show that the methods presented can effectively improve the gate breakdown voltage and greatly improve the reliability of the P-LDMOS.
A novel 2D analytical model for the doping profile of the bulk silicon RESURF LDMOS drift region is proposed. According to the proposed model, to obtain good performance, the doping profile in the total drift region of a RESURF LDMOS with a field plate should be piecewise linearly graded. The breakdown voltage of the proposed RESURF LDMOS with a piecewise linearly graded doping drift region is improved by 58. 8%, and the specific on-resistance is reduced by 87. 4% compared with conventional LDMOS. These results are verified by the two-dimensional process simulator Tsuprem-4 and the device simulator Medici.
