There is a great interest in monolithic 4H-SiC Junction Barrier Schottky （JBS） diodes with the capability of a high forward current for industrial power applications. In this paper, we report large-area monolithic 4H-SiC JBS diodes fabricated on a 10 μm 4H-SiC epitaxial layer doped to 6×1015 cm-3. JBS diodes with an active area of 30 mm2 had a forward current of up to 330 A at a forward voltage of 5 V, which corresponds to a current density of 1100 A/cm2. A near ideal breakdown voltage of 1.6 kV was also achieved for a reverse current of up to 100 gA through the use of an optimum multiple floating guard rings （MFGR） termination, which is about 87.2% of the theoretical value. The differential specific-on resistance （RSP-ON） was meas- ured to be 3.3 mΩcm2, leading to a FOM （VB2/RSP-ON） value of 0.78 GW/cm2, which is very close to the theoretical limit of the tradeoff between the specific-on resistance and breakdown voltage for 4H-SiC unipolar devices.
Based on the theoretical analysis of the 4H-SiC Schottky-barrier diodes （SBDs） with field plate termination, 4H-SiC SBD with semi-insulating polycrystalline silicon （SIPOS） FP termination has been fabricated. The relative dielectric con-stant of the SIPOS dielectric first used in 4H-SiC devices is 10.4, which is much higher than that of the SiO2 dielectric, leading to benefitting the performance of devices. The breakdown voltage of the fabricated SBD could reach 1200 V at leak-age current 20 μA, about 70% of the theoretical breakdown voltage. Meanwhile, both of the simulation and experimental results show that the length of the SIPOS FP termination is an important factor for structure design.
Field plate(FP)-terminated 4H-SiC trench gate MOSFETs are demonstrated in this work.N+/P?/N?/N+multiple epitaxial layers were grown on 3-inch N+type 4H-SiC substrate by chemical vapor deposition(CVD),and then the 4H-SiC trench gate MOSFETs were fabricated based on the standard trench transistor fabrication.Current-voltage measurements in forward and reverse bias have been performed on different devices with and without FP protections.It is found that more than 60%of the devices protected with FP termination are able to block 850 V.The measurements also show that the devices have the small leakage currents 0.15 nA at 600 V and 2.5 nA at 800 V,respectively.The experimental results also were compared with the simulated results,which show good agreement with each other in the trend.The limited performance of the devices is mainly because of the damage induced on the trench sidewalls from the etching process and the quality of the SiO2 films.Therefore,the 4H-SiC trench gate MOSFETs are expected to be optimized by reducing the etching damage and growing high-quality SiO2 dielectric films.
The fabrication of 4H-SiC vertical trench-gate metal-oxide-semiconductor field-effect transistors（UMOSFETs） is reported in this paper.The device has a 15-μm thick drift layer with 3×10^15 cm^-3 N-type doping concentration and a 3.1μm channel length.The measured on-state source-drain current density is 65.4 A/cm^2 at Vg = 40 V and VDS = 15 V.The measured threshold voltage（Vth） is 5.5 V by linear extrapolation from the transfer characteristics.A specific on-resistance（Rsp-on） is 181 mΩ·cm^2 at Vg = 40 V and a blocking voltage（BV） is 880 V（IDS = 100 μA@880V） at Vg = 0 V.
In this paper, the normally-off N-channel lateral 4H-SiC metal-oxide-semiconductor field-effect transistors （MOSF- FETs） have been fabricated and characterized. A sandwich- （nitridation-oxidation-nitridation） type process was used to grow the gate dielectric film to obtain high channel mobility. The interface properties of 4H-SiC/SiO2 were examined by the measurement of HF l-V, G-V, and C-V over a range of frequencies. The ideal C-V curve with little hysteresis and the frequency dispersion were observed. As a result, the interface state density near the conduction band edge of 4H-SiC was reduced to 2 x 1011 eV-l.cm-2, the breakdown field of the grown oxides was about 9.8 MV/cm, the median peak field- effect mobility is about 32.5 cm2.V-1 .s-1, and the maximum peak field-effect mobility of 38 cm2-V-1 .s-1 was achieved in fabricated lateral 4H-SiC MOSFFETs.
The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias stress（TDBS）,capacitance–voltage（C–V）,and secondary ion mass spectroscopy（SIMS）.It is revealed that two main categories of charge traps,near interface oxide traps（Nniot） and oxide traps（Not）,have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.
In this paper, 1.2 kV, 3.3 kV, and 5.0 kV class 4H-SiC power Schottky barrier diodes （SBDs） are fabricated with three N-type drift layer thickness values of 10 μm, 30μm, and 50 μm, respectively. The avalanche breakdown capabilities, static and transient characteristics of the fabricated devices are measured in detail and compared with the theoretical pre- dictions. It is found that the experimental results match well with the theoretical calculation results and are very close to the 4H-SiC theoretical limit line. The best achieved breakdown voltages （BVs） of the diodes on the 10 p.m, 30 m, and 50 -tm epilayers are 1400 V, 3320 V, and 5200 V, respectively. Differential specific-on resistances （Ron-sp） are 2.1 m--cm2, 7.34 mO. cm2, and 30.3 m-. cm2, respectively.
Near-interface oxide traps （NIOTs） in 4H-SiC metal-oxide-semiconductor （MOS） structures fabricated with and without annealing in NO are systematically investigated in this paper. The properties of NIOTs in SiC MOS structures prepared with and without annealing in NO are studied and compared in detail. Two main categories of the NIOTs, the “slow” and “fast” NIOTs, are revealed and extracted. The densities of the “fast” NIOTs are determined to be 0.761011 cm-2 and 0.471011 cm-2 for the N2 post oxidation annealing （POA） sample and NO POA sample, respectively. The densities of “slow” NIOTs are 0.791011 cm-2 and 9.441011 cm-2 for the NO POA sample and N2 POA sample, respectively. It is found that the NO POA process only can significantly reduce “slow” NIOTs. However, it has a little effect on “fast” NIOTs. The negative and positive constant voltage stresses （CVS） reveal that electrons captured by those “slow” NIOTs and bulk oxide traps （BOTs） are hardly emitted by the constant voltage stress.
The effect of the different re-oxidation annealing （ROA） processes on the SiO2/SiC interface charac- teristics has been investigated. With different annealing processes, the flat band voltage, effective dielectric charge density and interface trap density are obtained from the capacitance-voltage curves. It is found that the lowest interface trap density is obtained by the wet-oxidation annealing process at 1050 ℃ for 30 min, while a large num- ber of effective dielectric charges are generated. The components at the SiO2/SiC interface are analyzed by X-ray photoelectron spectroscopy （XPS） testing. It is found that the effective dielectric charges are generated due to the existence of the C and H atoms in the wet-oxidation annealing process.
Si C半超结垂直双扩散金属氧化物半导体场效应管(VDMOSFET)相对于常规VDMOSFET在相同导通电阻下具有更大击穿电压.在N型外延层上进行离子注入形成半超结结构中的P柱是制造Si C半超结VDMOSFET的关键工艺.本文通过二维数值仿真研究了离子注入导致的电荷失配对4H-Si C超结和半超结VDMOSFET击穿电压的影响,在电荷失配程度为30%时出现半超结VDMOSFET的最大击穿电压.在本文的器件参数下,P柱浓度偏差导致击穿电压降低15%时,半超结VDMOSFET柱区浓度偏差范围相对于超结VDMOSFET可提高69.5%,这意味着半超结VDMOSFET对柱区离子注入的控制要求更低,工艺制造难度更低.
