An inductorless wideband programmable-gain amplifier （PGA） for 60 GHz wireless transceivers is presented. To attain wideband characteristics, a modified Cherry-Hooper amplifier with a negative capacitive neu- tralization technique is employed as the gain cell while a novel circuit technique for gain adjustment is adopted; this technique can be universally applicable in wideband PGA design and greatly simplifying the design of wideband PGA. By cascading two gain cells and an output buffer stage, the PGA achieves the highest gain of 30 dB with the bandwidth much wider than 3 GHz. The PGA has been integrated into one whole 60 GHz wireless transceiver and implemented in the TSMC 65 nm CMOS process. The measurements on the receiver front-end show that the re- ceiver front-end achieves an 18 dB variable gain range with a 〉 3 GHz bandwidth, which proves the proposed PGA achieves an 18 dB variable gain range with a bandwidth much wider than 3 GHz. The PGA consumes 10.7 mW of power from a 1.2-V supply voltage with a core area of only 0.025 mm2.
A wideband on-chip millimeter-wave patch antenna in 0.18 μm CMOS with a low-resistivity （10 Ω.cm） silicon substrate is presented. The wideband is achieved by reducing the Q factor and exciting the high-order radiation modes with size optimization. The antenna uses an on-chip top layer metal as the patch and a probe station as the ground plane. The on-chip ground plane is connected to the probe station using the inner connection structure of the probe station for better performance. The simulated S11 is less than -10 dB over 46-95 GHz, which is well matched with the measured results over the available 40-67 GHz frequency range from our measurement equipment. A maximum gain of-5.55 dBi with 4% radiation efficiency at a 60 GHz point is also achieved based on Ansofi HFSS simulation. Compared with the current state-of-the-art devices, the presented antenna achieves a wider bandwidth and could be used in wideband millimeter-wave communication and image applications.
A reconfigurable complex band-pass （CBP）/low-pass （LP） active-RC filter with a noise-shaping technique for wireless receivers is presented. Its bandwidth is reconfigurable among 500 kHz, 1 MHz and 4 MHz in LP mode and 1 MHz, 2 MHz and 8 MHz in CBP mode with 3 MHz center frequency. The Op-Amps used in the filter are realized in cell arrays in order to obtain scalable power consumption among the different operation modes. Furthermore, the filter can be configured into the 1st order, 2nd order or 3rd order mode, thus achieving a flexible filtering property. The noise-shaping technique is introduced to suppress the flicker noise contribution. The filter has been implemented in 180 nm CMOS and consumes less than 3 mA in the 3rd 8 MHz-bandwidth CBP mode. The spot noise at 100 Hz can be reduced by 14.4 dB at most with the introduced noise-shaping technique.
A low-power wideband hybrid automatic gain control （AGC） loop for a GNSS receiver is presented. Single AGC in the I/Q path is composed of four-stage programmable gain amplifiers （PGAs）, a differential peak detector, two comparators, a control algorithm logic, a decoder and the reference voltage source. Besides being controlled by an AGC loop, the gain of PGAs could altematively be controlled by an off-chip digital baseband processor through the SPI interface. To obtain low power consumption and noise, an improved source degenerated amplifier is adopted, and the I/Q path phase mismatch within the ±5° range is calibrated with 0.2° accuracy. Implemented in 65 nm CMOS, the measured PGA total gains range from 9.8 to 59.5 dB with an average step of 0.95 dB and simulated bandwidth of more than 110 MHz. The settling time is about 180 μs with 80% AM input with measured signal power from -76.7 to -56.6 dBm from a radio-frequency amplifier （RFA） input port, and also reduces to 90 #s with clock frequency doubling. The single AGC consumes almost 0.8 mA current from the 2.5-V supply and occupies an area of 750 × 300 μm2.
