A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital converters （ADC）. Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.
In a time-interleaved analog-to-digital converter （TI ADC）, several individual ADCs operate in parallel to achieve a higher sampling rate. Low power consumption as well as good linearity can be obtained by applying successive approximation register （SAR） converters as sub-channel ADCs. In spite of the advantages, this structure suffers from three mismatches, which are offset mismatch, gain mismatch, and time skew. This paper focuses on a TI SAR ADC with a number of channels. The mismatch effects in the frequency domain are analyzed and the derived close form formulas are verified based on Matlab. In addition, we clarify that the standard deviation of DNL and INL of an M-channel TI ADC is reduced by a factor of ~ compared to a single channel ADC. The formulas can be used to derive the corresponding requirements when designing a TI ADC. Our analysis process is able to inform the study of calibration algorithms.
An ultra low voltage rectifier with high power conversion efficiency （PCE） for PE energy harvesting ap- plications is presented in this paper. This is achieved by utilizing the DTMOS which the body terminal is connected to the gate terminal in a diode connected transistor. This implementation facilitates the rectifier with dynamic con- trol over the threshold voltage. Moreover, we use input powered to take the place of output powered to reduce the power loss and thereby increasing the power conversion efficiency. Based on standard SMIC 0.18 μm CMOS tech- nology, the simulation results show that the voltage conversion efficiency and the power conversion efficiency can reach up to 90.5% and 95.5% respectively, when the input voltage equals to 0.2 V @ 100 Hz with load resistance 50 kW. Input voltages with frequencies in the range of 10 Hz-1 kHz can be rectified.
An energy-efficient and highly linear capacitor switching procedure for successive approximation regis- ter （SAR） ADCs is presented. The proposed switching procedure achieves 37% less switching energy when compared to the well-known VcM-based switching scheme. Moreover, the proposed method shows better linearity than the VcM-based one. The proposed switching procedure is applied to a 10-bit 1.0 V 300 kS/s SAR ADC implemented in 0.18μm standard CMOS. The measured results show the SAR ADC achieves an SNDR of 55.48 dB, SFDR of 66.98 dB, and consumes 2.13 μW at a 1.0 V power supply, resulting in a figure-of-merit of 14.66 fJ/conversion- step. The measured peak DNL and 1NL are 0.52/-0.47 LSB and 0.72/-0.79 LSB, respectively, and the peak INL 1 is observed at 4^-1 VFS and 4^-3 VFS, the same as the static nonlinearity model.
Based on the research of population migration algorithms （PMAs）, a population migration genetic algo- rithm （PMGA） is proposed, combining a PMA with a genetic algorithm. A scheme of area and power optimization for a ternary FPRM circuit is proposed by using the PMGA. Firstly, according to the ternary FPRM logic function expression, area and power estimation models are established. Secondly, the PMGA is used to search for the best area and power polarity. Finally, 10 MCNC Benchmark circuits are used to verify the effectiveness of the proposed method. The results show that the ternary FPRM circuits optimized by the PMGA saved 13.33% area and 20.00% power on average than the corresponding FPRM circuits optimized by a whole annealing genetic algorithm.
By researching the ternary flip-tlop and the adiabatic Domino circuit,a novel design of low-power ternary Domino JKL flip-flop on the switch level is proposed.First,the switch-level structure of the ternary adiabatic Domino JKL flip-flop is derived according to the switch-signal theory and its truth table.Then the ternary loop operation circuit and ternary reverse loop operation circuit are achieved by employing the ternary JKL tlip-tlop. Finally,the circuit is simulated by using the Spice tool and the results show that the logic function is correct. The energy consumption of the ternary adiabatic Domino JKL flip-flop is 69%less than its conventional Domino counterpart.
A high efficiency, high power factor, and linear constant current LED driver based on adaptive seg- mented linear architecture is presented. When the input voltage varied, the proposed LED driver automatically switched over LED strings according to the segmented LED voltage drop, which increased the LED lighting time. The efficiency and power factor are improved, while the system design is simplified by this control scheme. Without the usage of electrolytic capacitor and magnetic components, the proposed driver possesses advantages of smaller size, longer lifetime and lower cost over others. The proposed driver is implemented in 0.8 μm 5 V/40 V HVCMOS process, which occupies an active area of 820× 920μm2. The measured results show that the average value of the internal reference voltage is 500 4- 7 mV, with a standard deviation of only 4.629 mV, thus LED current can be set accurately. Under 220 V root mean square 50 Hz utility voltage and the number ratio of the three LED strings being 47 ： 17 ： 16, the system can realize a high power factor of 0.974 and power conversion efficiency of 93.4%.
A programmable high precision multiplying DAC （MDAC） is proposed. The MDAC incorporates a frequency-current converter （FCC） to adjust the power versus sampling rate and a programmable operational am- plifier （POTA） to achieve the tradeoff between resolution and power of the MDAC, which makes the MDAC suitable for a 12 bit SHA-less pipelined ADC. The prototype of the proposed pipelined ADC is implemented in an SMIC CMOS 0.18 μm 1P6M process. Experimental results demonstrate that power of the proposed ADC varies from 15.4 mW （10 MHz） to 63 mW （100 MHz） while maintaining an SNDR of 60.5 to 63 dB at all sampling rates. The differential nonlinearity and integral nonlinearity without any calibration are no more than 2.2/-1 LSB and 1.6/-1.9 LSB, respectively.
A 0.1-1.5 GHz, 3.07 pS root mean squares （RMS）jitter, area efficient phase locked loop （PLL） with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter （LPF） is significantly decreased by implementing a dual path charge pump （CP） technique in this PLL. Subject to specified power con- sumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator （VCO）, CP and phase/frequency detector （PFD） in order to minimize clock jitter. This method could improve 3-6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal-oxide-metal （MOM） capacitor, occupies 0.05 mm2 silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is -102 dBc/Hz @ 1 MHz offset frequency.
A 10-bit 50 MS/s pipelined SAR ADC is presented which pipelines a 5-bit SAR-based MDAC with a 6-bit SAR ADC.The 1-bit redundancy relaxes the requirement for the sub-ADC decision in accuracy.The SAR-based and ＂half-gain＂ MDAC reduce the power consumption and core area.The dynamic comparator and SAR control logic are applied to reduce power consumption.Implemented in 180 nm CMOS,the fabricated ADC achieves 56.04 dB SNDR and 5mW power consumption from 1.8 V power supply at 50 MS/s.
