Sb rich Ge_(2)Sb_(5)Te_(5) materials are investigated for use as the storage medium for high-speed phase change memory(PCM).Compared with conventional Ge2Sb2Te5,Ge_(2)Sb_(5)Te_(5) films have a higher crystallisation temperature(~200℃),larger crystallisation activation energy(3.13 eV),and a better data retention ability(100.2℃ for ten years).A reversible switching between set and reset states can be realised by an electric pulse as short as 5 ns for Ge_(2)Sb_(5)Te_(5)-based PCM cells,over 10 times faster than the Ge_(2)Sb_(5)Te_(5)-based one.In addition,Ge2Sb2Te5 shows a good endurance up to 3×10^(6) cycles with a resistance ratio of about three orders of magnitude.This work clearly reveals the highly promising potential of Ge_(2)Sb_(5)Te_(5) films for applications in high-speed PCM.
Phase change random access memory （PCRAM） is one of the best candidates for next generation non- volatile memory, and phase change SiESbETe5 material is expected to be a promising material for PCRAM. In the fabrication of phase change random access memories, the etching process is a critical step. In this paper, the etching characteristics of Si2Sb2Te5 films were studied with a CF4/Ar gas mixture using a reactive ion etching system. We observed a monotonic decrease in etch rate with decreasing CF4 concentration, meanwhile, Ar concentration went up and smoother etched surfaces were obtained. It proves that CF4 determines the etch rate while Ar plays an im- portant role in defining the smoothness of the etched surface and sidewall edge acuity. Compared with GeESbETe5, it is found that Si2Sb2Te5 has a greater etch rate. Etching characteristics of Si2SbETe5 as a function of power and pressure were also studied. The smoothest surfaces and most vertical sidewalls were achieved using a CF4/Ar gas mixture ratio of 10/40, a background pressure of 40 mTorr, and power of 200 W.
The dry etching characteristic of AlSbTe film was investigated by using a CF/Ar gas mixture.The experimental control parameters were gas flow rate into the chamber,CF/Ar ratio,the Oaddition,the chamber background pressure,and the incident RF power applied to the lower electrode.The total flow rate was 50 sccm and the behavior of etch rate of AlSbTe thin films was investigated as a function of the CF/Ar ratio,the Oaddition,the chamber background pressure,and the incident RF power.Then the parameters were optimized.The fast etch rate was up to 70.8 nm/min and a smooth surface was achieved using optimized etching parameters of CFconcentration of 4%,power of 300 W and pressure of 80 mTorr.
A fully integrated low-jitter, precise frequency CMOS phase-locked loop （PLL） clock for the phase change memory （PCM） drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector （PFD） with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator （VCO）, a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 #m CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM＇s program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.
Phase-change line memory cells with different line widths are fabricated using focused-ion-beam deposited C-Pt as a hard mask. The electrical performance of these memory devices was characterized. The current^oltage （I-V） and resistance-voltage （RV） characteristics demonstrate that the power consumption decreases with the width of the phase-change line. A three-dimensional simulation is carried out to further study the scaling properties of the phase- change line memory. The results show that the resistive amorphous （RESET） power consumption is proportional to the cross-sectional area of the phase-change line, but increases as the line length decreases.
Along with a series of research works on the physical prototype and properties of the memory cell,an SPICE model for phase-change memory（PCM） simulations based on Verilog-A language is presented.By handling it with the heat distribution algorithm,threshold switching theory and the crystallization kinetic model,the proposed SPICE model can effectively reproduce the physical behaviors of the phase-change memory cell.In particular,it can emulate the cell＇s temperature curve and crystallinity profile during the programming process,which can enable us to clearly understand the PCM＇s working principle and program process.
A low ripple switched capacitor charge pump applicable to phase change memory （PCM） is presented. For high power efficiency, the selected charge pump topology can automatically change the power conversion ratio between 2X/1.5X modes with the input voltage. For a low output ripple, a novel operation mode is used. Compared with the conventional switched capacitor charge pump, the flying capacitor of the proposed charge pump is charged to Vo- 14n during the charge phase （Vo is the prospective output voltage）. In the discharge phase, the flying capacitor is placed in series with the Vin to transfer energy to the output, so the output voltage is regulated at Vo. A simulation was implemented for a DC input range of 1.6-2.1 V in on SMIC standard 40 nm CMOS process, the result shows that the new operation mode could regulate the output of about 2.5 V with a load condition from 0 to 10 mA, and the ripple voltage is lower than 4 mV. The maximum power efficiency reaches 91%.
In this paper, chemical mechanical planarization （CMP） of amorphous Ge2Sb2Te5 （a-GST） in acidic H2O2 slurry is investigated. It was found that the removal rate of a-GST is strongly dependent on H2O2 concentration and gradually increases with the increase in H2O2 concentration, but the static etch rate first increases and then slowly decreases with the increase in H2O2 concentration. To understand the chemical reaction behavior of H2O2 on the a-GST surface, the potentiodynamic polarization curve, surface morphology and cross-section of a-GST immersed in acidic slurry are measured and the results reveal that a-GST exhibits a from active to passive behavior for from low to high concentration of H2O2. Finally, a possible removal mechanism of a-GST in different concentrations of H2O2 in the acidic slurry is described.
The results of adhesion improvement and SET-RESET operation voltage reduction for the GeN buffer layer are presented.It is found that the adhesive strength between the Ge_(2)Sb_(2)Te_(5)(GST)layer and the layer below could be increased at least 20 times,which is beneficial for solving the phase change material peeling issue in the fabrication process of phase change memory(PCM).Meanwhile,the RESET voltage of the PCM cell with a 3-nm-thick GeN buffer layer can be reduced from 3.5 V to 2.2 V.The GeN buffer layer will play an important role in high density and low power consumption PCM applications.
