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国家自然科学基金(61036004)

作品数:23 被引量:31H指数:3
相关作者:徐江涛姚素英高静聂凯明李斌桥更多>>
相关机构:天津大学更多>>
发文基金:国家自然科学基金天津市应用基础与前沿技术研究计划广东省自然科学基金更多>>
相关领域:电子电信自动化与计算机技术化学工程更多>>

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23 条 记 录,以下是 1-10
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适于高级数TDI CMOS图像传感器的模拟累加器的研究被引量:1
2016年
分析并解决了应用于TDI CMOS图像传感器的模拟累加器的寄生问题.设计中加入了去耦开关,通过引入交流地来消除积分器内的寄生.此外,采用正反馈电容,在积分阶段注入补偿电荷,来补偿无法消除的寄生所带来的影响.在设计中采用0.18μm工艺,供电电压为3.3 V.仿真结果表明,累加器所能提升的信噪比从17.835 d B增加到了21.068 d B,整体线性度达到了99.7%.
黄福军徐江涛聂凯明
关键词:CMOS图像传感器时间延迟积分累加器信噪比
一种适用于16级TDI CMOS图像传感器的电流型累加器(英文)
2013年
提出一种适用于混合域累加的16级时间延迟积分(Time Delay Integration,TDI)型CMOS图像传感器的电流型累加器.为了实现混合域的累加,电流信号首先在电流型累加器中累加4次,累加的结果被量化成数字量后再次完成4次的累加,即4×4的混合累加模式.详细分析了电流型累加器的热噪声和闪烁噪声特性,并给出了等效输入噪声的均方根电压表达式,并结合仿真工具进行分析验证.提出的电流型累加器电路在CMOS180nm 1.8V供电电源的工艺下实现,电路的功耗为0.37mW,芯片面积为0.03mm×0.82mm.经过电流型累加器的4次累加后,能够将信号的信噪比提升5.86dB.
高岑姚素英高静
关键词:读出电路CMOS图像传感器
A Single-Transistor Active Pixel CMOS Image Sensor Architecture被引量:1
2012年
A single-transistor CMOS active pixel image sensor(1T CMOS APS)architecture is proposed,By switching the photosensing pinned diode,resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower.Thus,the reset and selected transistors can be removed.In addition,the reset and selected signal lines can be shared to reduce the metal signal line,leading to a very high fill factor.The pixel design and operation principles are discussed in detail.The functionality of the proposed 1 T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35μm CMOS AMIS technology.
章国安张东维何进苏艳梅王承陈沁梁海浪叶韵
关键词:ACTIVERESET
Complete Focal Plane Compression Based on CMOS Image Sensor Using Predictive Coding
2015年
In this paper, a CMOS image sensor(CIS) is proposed, which can accomplish both decorrelation and entropy coding of image compression directly on the focal plane. The design is based on predictive coding for image decorrelation. The predictions are performed in analog domain by 2×2 pixel units. Both the prediction residuals and original pixel values are quantized and encoded in parallel. Since the residuals have a peak distribution around zero,the output codewords can be replaced by the valid part of the residuals' binary mode. The compressed bit stream is accessible directly at the output of CIS without extra disposition. Simulation results show that the proposed approach achieves a compression rate of 2. 2 and PSNR of 51 on different test images.
姚素英于潇高静徐江涛
关键词:CMOS图像传感器焦平面二进制模式编码图像
20 MHz Switched-Current Sample-and-Hold Circuit with Low Charge Injection
2013年
A switched-current sample-and-hold circuit with low charge injection was proposed. To obtain low noise and charge injection, the zero-voltage switching was used to remove the signal-dependent charge injection, and the signal-independent charge injection was reduced by removing the feed-through voltage from the input port of the memory transistor directly. This current sample-and-hold circuit was implemented using CMOS 180 nm 1.8 V technology. For a 0.8 MHz sinusoidal signal input, the simulated signal-to-noise and distortion ratio and total harmonic distortion were improved from 53.74 dB and -51.24 dB to 56.53 dB and -54.36 dB at the sampling rate of 20 MHz respectively, with accuracy of 9.01 bit and power consumption of 0.44 mW.
高岑姚素英高静
关键词:零电压开关电荷注入电流采样总谐波失真
A Comparative Study of Ballistic Transport Models for Nanowire MOSFETs
2013年
We comparatively study two representative ballistic transport models of nanowire metal-oxide-semiconductor field effect transistors,i.e.the Natori model and the Jiménez model.The limitations and applicability of both the models are discussed.Then the Jiménez model is extended to include atomic dispersion relations and is compared with the Natori model from the aspects of ballistic current and quantum capacitance.It is found that the Jiménez model can produce similar results compared with the more complex Natori model even at very small nanowire dimensions.
张立宁梅金河张香煜陶金胡月何进陈文新
关键词:MOSFETSCAPACITANCEDISPERSION
基于平衡态的动态比较器失调电压分析和设计优化
2012年
本文提出了一种基于平衡态的动态比较器失调电压分析设计技术。以两支路电压电流相等的平衡态为分析基础,通过在复位电压跳变时刻引入补偿电压的方法,逐一分析了动态比较器各晶体管参数对总体失调电压的影响,建立了失调电压的数学模型;采用Chartered 0.18um1P6M工艺对Lewis-Gray型动态比较器进行了电路和版图设计,并利用可快速提取失调电压的定步长仿真方法对其失调电压进行了仿真,结果表明所提出的分析方法可以相对准确的估算失调电压。以该分析方法为基础,本文还提出一种基于总体失调电压影响权重的晶体管分组优化方法,在保证总体面积不变的条件下,可将失调电压有效降低50%以上。经流片测试结果表明,本文所提出的分析和优化方法可应用于高速高精度系统中比较器的设计。
巫朝发姚素英赵士彬高静徐江涛
关键词:动态比较器失调电压
10-Bit Single-Slope ADC with Error Calibration for TDI CMOS Image Sensor
2013年
A 10-bit single-slope analog-to-digital converter (ADC) for time-delay-integration CMOS image sensor was proposed. A programmable ramp generator was applied to accomplish the error calibration and improve the linearity. The ADC was fabricated in a 180 nm 1P4M CMOS process. Experimental results indicate that the differential nonlinearity and integral nonlinearity were 0.51/-0.53 LSB and 0.63/-0.71 LSB, respectively. The sampling rate of the ADC was 32 kHz.
高岑姚素英杨志勋高静徐江涛
关键词:ADCTDI积分非线性微分非线性
A nano-metallic-particles-based CMOS image sensor for DNA detection被引量:1
2012年
In this paper we report on a study of the CMOS image sensor detection of DNA based on self-assembled nano-metallic particles, which are selectively deposited on the surface of the passive image sensor. The nano-metallic particles effectively block the optical radiation in the visible spectrum of ordinary light source. When such a technical method is applied to DNA detection, the requirement for a special UV light source in the most popular fluorescence is eliminated. The DNA detection methodology is tested on a CMOS sensor chip fabricated using a standard 0.5 μm CMOS process. It is demonstrated that the approach is highly selective to detecting even a signal-base mismatched DNA target with an extremely-low-concentration DNA sample down to 10 pM under an ordinary light source.
何进苏艳梅马玉涛陈沁王若楠叶韵马勇梁海浪
关键词:DNA检测纳米金属粒子金属纳米颗粒CMOS工艺
用于时间延迟积分型图像传感器的流水采样列级运放共享累加器
2015年
提出了一种适用于TDI-CIS(时间延迟积分CMOS图像传感器)的模拟域流水采样列级运放共享累加器结构。提出的这种模拟累加器结构应用流水采样结构在不改变运放速率的前提下,将累加器的速率提升为传统累加器的2倍;采用积分电容列运放共享技术将n级TDI-CIS所需的运放个数减少至采用传统累加器所需个数的1/n。分析了流水采样累加器结构的原理以及输出噪声。使用标准0.18μm CMOS工艺进行了电路设计。仿真结果显示,提出的模拟累加器结构功耗为0.29m W,采样率为2 Msample/s。结果表明流水采样列级运放共享累加器结构在保持低电路面积和功耗的同时,可将TDI-CIS最大可达到的行频增加一倍,更适于高速扫描的应用环境。
夏雨姚素英聂凯明徐江涛
关键词:CMOS图像传感器时间延迟积分运放共享
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