This paper proposes a low power wake-up baseband circuit used in Chinese Electronic Toll Collection (ETC) system. To reduce the static power consumption, a low power biasing strategy is proposed. The proposed circuit is fabricated in TSMC 0.18 μm technology with an area of 0.09 mm 2 . Its current consumption is only 2.1 μA under 1.8 V power supply. It achieves a sensitivity of 0.95 mV at room temperature with a variation of only ±28% over -35℃ to 105℃.
A multimode DLL with trade-off between multiphase and static phase error is presented. By adopting a multimode control circuit to regroup the delay line, a better static phase error performance can be achieved while reducing the number of output phases. The DLL accomplishes three operation modes: mode1 with a four-phase output, mode2 with a two-phase output and a better static phase error performance, and mode3 with only a onephase output but the best static phase error performance. The proposed DLL has been fabricated in 0.13 m CMOS technology and measurement results show that the static phase errors of mode1, mode2 and mode3 are –18.2 ps,11.8 ps and 6:44 ps, respectively, at 200 MHz. The measured RMS and peak-to-peak jitters of mode1, mode2 and mode3 are 2.0 ps, 2.2 ps, 2.1 ps and 10 ps, 9.3 ps, 10 ps respectively.
This paper proposes a 12-bit,40-Ms/s pipelined analog-to-digital converter(ADC) with an improved high-gain and wide-bandwidth operational amplifier(opamp).Based on the architecture of the proposed ADC,the non-ideal factors of opamps are first analyzed,which have the significant impact on the ADC's resolution.Then,the compensation techniques of the ADC's opamp are presented to restrain the negative effect introduced by the gainboosting technique and switched-capacitor common-mode-feedback structure.After analysis and optimization,the ADC implemented in a 0.35μm standard CMOS process shows a maximum signal-to-noise distortion ratio of 60.5 dB and a spurious-free dynamic range of 74.5 dB,respectively,at a 40 MHz sample clock with over 2 Vpp input range.
该文对开关电容式闭环微加速度计的系统稳定性进行了深入研究。提出了可通用于该类微传感系统的动态特性分析方法,并具体研究了传感器品质因子、力反馈延迟、电路补偿单元的参数多种因素对系统稳定性的影响。基于0.35 mm CMOS工艺实现了一款接口电路芯片实例,实验结果表明,充分的电路补偿设计对于保证系统稳定性十分关键,实际的系统稳定边界与理论分析结果也较为吻合,从而证明了理论分析方法的正确性。
This paper presents a charge-sensitive-amplifier(CSA)based readout circuit for capacitive microelectro-mechanical-system(MEMS)sensors.A continuous-time(CT)readout structure using the chopper technique is adopted to cancel the low frequency noise and improve the resolution of the readout circuits.An operational trans-conductance amplifier(OTA)structure with an auxiliary common-mode-feedback-OTA is proposed in the fully differential CSA to suppress the chopper modulation induced disturbance at the OTA input terminal.An analog temperature compensation method is proposed,which adjusts the chopper signal amplitude with temperature variation to compensate the temperature drift of the CSA readout sensitivity.The chip is designed and implemented in a 0.35 m CMOS process and is 2.1 2.1 mm2in area.The measurement shows that the readout circuitachieves0.9aF/√Hz capacitive resolution,97dBd ynamic range in 100Hz signal bandwidth,and 0.8mV/fF sensitivity with a temperature drift of 35 ppm/℃ after optimized compensation.
