The impedance characteristics of distributed amplifiers are analyzed based on T-type matching networks, and a distributed power amplifier consisting of three gain cells is proposed. Non-uniform T-type matching networks are adopted to make the impedance of artificial transmission lines connected to the gate and drain change stage by stage gradually, which provides good impedance matching and improves the output power and efficiency. The measurement results show that the amplifier gives an average forward gain of 6 dB from 3 to 16. 5 GHz. In the desired band, the input return loss is typically less than - 9. 5 dB, and the output return loss is better than -8.5 dB. The output power at 1-dB gain compression point is from 3.6 to 10. 6 dBm in the band of 2 to 16 GHz while the power added efficiency （PAE） is from 2% to 12. 5% . The power consumption of the amplifier is 81 mW with a supply of 1.8 V, and the chip area is 0.91 mm × 0.45 mm.
A low noise distributed amplifier consisting of 9 gain cells is presented.The chip is fabricated with 0.15-μm GaAs pseudomorphic high electron mobility transistor（PHEMT） technology from Win Semiconductor of Taiwan.A special optional gate bias technique is introduced to allow an adjustable gain control range of 10 dB.A novel cascode structure is adopted to extend the output voltage and bandwidth.The measurement results show that the amplifier gives an average gain of 15 dB with a gain flatness of±1 dB in the 2-20 GHz band.The noise figure is between 2 and 4.1 dB during the band from 2 to 20 GHz.The amplifier also provides 13.8 dBm of output power at a 1 dB gain compression point and 10.5 dBm of input third order intercept point（IIP3）,which demonstrates the excellent performance of linearity.The power consumption is 300 mW with a supply of 5 V,and the chip area is 2.36×1.01 mm^2.
A novel design and optimization method for distributed amplifiers(DAs)is proposed to make the circuit design more convenient and efficient.This method combines artificial intelligence(AI)optimization with manual design by two loops,i.e.,outer manual loop and inner AI loop.The layout design is followed by AI optimization to take more influencing factors such as parasitic effect into account for the practicability.A DA with three gain cells is designed and optimized in a standard 0.18μm complementary metal-oxide-semiconductor(CMOS)technology to verify the proposed method.With a chip area of only 0.55 mm2,the DA provides 9.8 dB average forward gain from 1 to 15.2 GHz.The output power at 1 dB output compression point is more than 7.7 dBm in the 2-14 GHz frequency band and the peak power-added efficiency(PAE)is 10.6%.The measurement results validate the proposed method as a robust DA design procedure for improving circuit performance and design efficiency.
