The multi-step rapid thermal annealing process of Ti/Al/Ni/Au can make good ohmic contacts with both low contact resistance and smooth surface morphology for AlGaN/GaN HEMTs.In this work,the mechanism of the multi-step annealing process is analyzed in detail by specific experimental methods.The experimental results show that annealing temperature and time are very important parameters when optimizing the Ti/Al layer for lower resistance and the Ni/Au layer for smooth surface morphology.It is very important for good ohmic contacts to balance the rate of various reactions by adjusting the annealing temperature and time.We obtained a minimum specific contact resistance of 3.22×10^（17）Ω·cm^2 on the un-doped AlGaN/GaN structure with an optimized multistep annealing process.
Comparisons are performed to study the drive current of accumulation-mode（AM） p-channel wrap-gated Fin-FETs.The drive current of the AM p-channel FET is 15%-26%larger than that of the inversion-mode （IM） p-channel FET with the same wrap-gated fin channel,because of the body current component in the AM FET, which becomes less dominative as the gate overdrive becomes larger.The drive currents of the AM p-channel wrap-gated Fin-FETs are 50%larger than those of the AM p-channel planar FETs,which arises from effective conducting surface broadening and volume accumulation in the AM wrap-gated Fin-FETs.The effective conducting surface broadening is due to wrap-gate-induced multi-surface conduction,while the volume accumulation,namely the majority carrier concentration anywhere in the fin cross section exceeding the fin doping density,is due to the coupling of electric fields from different parts of the wrap gate.Moreover,for AM p-channel wrap-gated Fin-FETs, the current in channel along 110 is larger than that in channel along 100,which arises from the surface mobility difference due to different transport directions and surface orientations.That is more obvious as the gate overdrive becomes larger,when the surface current component plays a more dominative role in the total current.
Silicon junctionless nanowire transistor（JNT） is fabricated by femtosecond laser direct writing on a heavily n-doped SOI substrate.The performances of the transistor,i.e.,current drive,threshold voltage,subthreshold swing（SS）,and electron mobility are evaluated.The device shows good gate control ability and low-temperature instability in a temperature range from 10 K to 300 K.The drain currents increasing by steps with the gate voltage are clearly observed from 10 K to50 K,which is attributed to the electron transport through one-dimensional（1D） subbands formed in the nanowire.Besides,the device exhibits a better low-field electron mobility of 290 cm2·V-1·s-1,implying that the silicon nanowires fabricated by femtosecond laser have good electrical properties.This approach provides a potential application for nanoscale device patterning.
We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. The conductivity of the accumulation region is totally suppressed when the gate voltage is more positive than the flatband voltage. The extracted low field electron mobility in the accumulation layer is estimated to be 1.25 cm^2·V^-1·s^-1. A time-dependent drain current measured at 6 K predicts the existence of a complex trap state at the Si–Si O2 interface within the bandgap. The suppressed drain current and comparable low electron mobility of the accumulation layer can be well described by the large Coulomb scattering arising from the presence of a large density of interface charged traps. The effects of charge trapping and the scattering at interface states become the main reasons for mobility reduction for electrons in the accumulation region.
Single and multiple n-channel junctionless nanowire transistors （JNTs） are fabricated and experimentally investigated at variable temperatures. Clear current oscillations caused by the quantum-confinement effect are observed in the curve of drain current versus gate voltage acquired at low temperatures （10 K-100 K） and variable drain bias voltages （10 mV- 90 mV）. Transfer characteristics exhibit current oscillation peaks below flat-band voltage （VFB） at temperatures up to 75 K, which is possibly due to Coulomb-blocking from quantum dots, which are randomly formed by ionized dopants in the just opened n-type one-dimensional （1D） channel of silicon nanowires. However, at higher voltages than VFB, regular current steps are observed in single-channel JNTs, which corresponds to the fully populated subbands in the 1D channel. The subband energy spacing extracted from transconductance peaks accords well with theoretical predication. However, in multiple-channel JNT, only tiny oscillation peaks of the drain current are observed due to the combination of the drain current from multiple channels with quantum-confinement effects.
