A highly configurable fast Fourier transform intellectual property core (FFT IP core) that can be mounted on Avalon bus of Nios II processor is designed in this paper, by the means of custombuilt components in SOPC Builder. Not only the data number can be configured to 2n and the data width can be configured as integer or floating-point number of 32 bits, but also the number of inner butterfly units is configurable, which can effectively resolve the contradiction between speed and hardware resource occupancy. The IP core is designed by butterfly computing elements of a mixed radix-4 and radix-2 algorithm and applies the inplace addressing scheme and reusing method to reduce hard-ware resources consumption. Functional simulation by Quartus Ⅱplatform proves that the results calculated by FFT IP core are ac-cordant with the Matlab results. Hardware test on DE2 development board by timestamp timer demonstrates that the FFT IP core costs only 34.8 μs to achieve FFT of 512 sampled data with precision of 32-bit floating point. It is demonstrated that the IP core has the advantages of feasible configuration, easy use, and high precision.
LIU SanjunSUN LinjiaoLI ShaowuYI JinqiaoMIAO Yuzhuang
无人机三维航迹规划由于规划约束众多,同时面临在巨大的搜索空间中寻优,往往规划速度慢,规划效率低.结合二维规划和高度规划实现三维规划是一种有效提升规划速度的解决方案,在利用Fast M arching Method(FMM)进行二维规划的基础上,采用Sparse A-star(SAS)搜索算法进行高度规划,分阶段考虑航迹规划的各种环境约束和机动约束,从而压缩规划空间.实验表明,该方法航迹规划速度快,所得到的三维航迹具有良好的地形跟随能力和避障能力.
