An ultra-low specific on-resistance（R_（on,sp）） integrated silicon-on-insulator（SOI） double-gate triple RESURF（reduced surface field） n-type MOSFET（DG T-RESURF） is proposed.The MOSFET features two structures： an integrated double gates structure（DG） that combines a planar gate with an extended trench gate,and a p-type buried layer（BP） in the n-type drift region.First,the DG forms dual conduction channels and shortens the forward current path,so reducing R_（on,sp）.The DG works as a vertical field plate to improve the breakdown voltage （BV） characteristics.Second,the BP forms a triple RESURF structure（T-RESURF）,which not only increases the drift doping concentration but also modulates the electric field.This results in a reduced R_（on,sp） and an improved BV.Third,the extended trench gate and the BP linked with the p-body region reduce the sensitivity of the BV to position of the BP.The BV of 325 V and R_（on,sp） of 8.6 mΩ·cm^2 are obtained for the DG T-RESURF by simulation. R_（on,sp） of DG T-RESURF is decreased by 63.4%in comparison with a planar-gate single RESURF MOSFET（PG S-RESURF）,and the BV is increased by 9.8%.
A low on-resistance （Ron,sp） integrable silicon-on-insulator （SOI） n-channel lateral double-diffused metal-oxide-semiconductor （LDMOS） is proposed and its mechanism is investigated by simulation. The LDMOS has two features： the integration of a planar gate and an extended trench gate （double gates （DGs））; and a buried P-layer in the N-drift region, which forms a triple reduced surface field （RESURF） （TR） structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance （Ron,sp） and an improved breakdown voltage （BV） in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm^2, respectively, for a DG TR metal-oxide semiconductor field-effect transistor （MOSFET） by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.
A low specific on-resistance （RS,on） silicon-on-insulator （SOI） trench MOSFET （nmtal-oxide-semiconductor-field- effect-transistor） with a reduced cell pitch is proposed. The lateral MOSFET features multiple trenches： two oxide trenches in the drift region and a trench gate extended to the buried oxide （BOX） （SOI MT MOSFET）. Firstly, the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si; secondly, the oxide trenches cause multiple=directional depletion, which improves the electric field distribution and enhances the reduced surface field （RESURF） effect in the SOI layer. Both of them result in a high breakdown voltage （BV）. Thirdly, the oxide trenches cause the drift region to be folded in the vertical direction, leading to a shortened cell pitch and a reduced Rs,on. Fourthly, the trench gate extended to the BOX further reduces RS,on, owing to the electron accumulation layer. The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor （LDMOS） to 632 V at the same half cell pitch of 21.5 μm, and RS,on decreases from 419 mΩ cm2 to 36.6 mΩ. cm2. The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.
A novel partial silicon-on-insulator （PSOI） high voltage device with a low-k （relative permittivity） dielectric buried layer （LK PSOI） and its breakdown mechanism are presented and investigated by MEDICI. At a low k value the electric field strength in the dielectric buried layer （EI） is enhanced and a Si window makes the substrate share the vertical drop, resulting in a high vertical breakdown voltage; in the lateral direction, a high electric field peak is introduced at the Si window, which modulates the electric field distribution in the SOI layer; consequently, a high breakdown voltage （BV） is obtained. The values of EI and BV of LK PSOI with ki = 2 on a 2μm thick SOI layer over 1μm thick buried layer are enhanced by 74% and 19%, respectively, compared with those of the conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect.
An SOI LDMOS with a compound buried layer（CBL） was proposed.The CBL consists of an upper buried oxide layer（UBOX） with a Si window and two oxide steps,a polysilicon layer and a lower buried oxide layer （LBOX）.In the blocking state,the electric field strengths in the UBOX and LBOX are increased from 88 V/μm of the buried oxide（BOX） in a conventional SOI（C-SOI） LDMOS to 163 V/μm and 460 V/μm by the holes located on the top interfaces of the UBOX and LBOX,respectively.Compared with the C-SOI LDMOS,the CBL LDMOS increases the breakdown voltage from 477 to 847 V,and lowers the maximal temperature by 6 K.
A novel triple RESURF（T-resurf） SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and leading to a high drift doping and a low on-resistance.Secondly,at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side,which results in uniform bulk electric field distributions and an enhanced BV.The proposed structure is used in SOI devices for the first time.The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6μm-thick SOI layer over a 2μm-thick buried oxide layer,and its R_（sp） is reduced from 16.5 to 13.8 mΩ·cm^2 in comparison with the double RESURF（D-resurf） SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV^2/R_（on）.It reduces R_（sp） by 25%in 400 V SOI LDMOS and by 38%in 550 V SOI LDMOS compared with the D-resurf structure.
A new lateral insulated-gate bipolar transistor（LIGBT） with a SiO_2 shielded layer anode on SOI substrate is proposed and discussed.Compared to the conventional LIGBT,the proposed device offers an enhanced conductivity modulation effect due to the SiO_2 shielded layer anode structure which can be formed by SIMOX technology.Simulation results show that,for the proposed LIGBT,during the conducting state,the electron-hole plasma concentrations in the n-drift region are several times larger than those of the conventional LIGBT;the conducting current is up to 37% larger than that of the conventional one.The enhanced conductivity modulation effect by SiO_2 shielded layer anode does not sacrifice other characteristics of the device,such as breakdown and switching,but is compatible with other optimized technologies.
A new partial SOI （silion-on-insulator） （PSOI） high voltage P-channel LDMOS （lateral double-diffused metal-oxide semiconductor） with an interface hole islands （HI） layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field （Er） in the dielectric buried oxide layer （BOX） and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage （BV）. The values of E1 and BV of an HI PSOI with a 2-~m thick SOI layer over a 1-~tm thick buried layer are 580V/~m and -582 V, respectively, compared with 81.5 V/p.m and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect （SHE）. Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.
This paper proposes a new n＋-charge island （NCI） P-channel lateral double diffused metal-oxide semiconductor （LDMOS） based on silicon epitaxial separation by implantation oxygen （E-SIMOX） substrate. Higher concentration self-adapted holes resulting from a vertical electric field are located in the spacing of two neighbouring n＋-regions on the interface of a buried oxide layer, and therefore the electric field of a dielectric buried layer （EI） is enhanced by these holes effectively, leading to an improved breakdown voltage （BV）. The VB and E! of the NCI P-channel LDMOS increase to -188 V and 502.3 V/μm from -75 V and 82.2 V/μm of the conventional P-channel LDMOS with the same thicknesses SOI layer and the buried oxide layer, respectively. The influences of structure parameters on the proposed device characteristics are investigated by simulation. Moreover, compared with the conventional device, the proposed device exhibits low special on-resistance.
This paper presents a novel high-voltage lateral double diffused metal-oxide semiconductor （LDMOS） with self- adaptive interface charge （SAC） layer and its physical model of the vertical interface electric field. The SAC can be self-adaptive to collect high concentration dynamic inversion holes, which effectively enhance the electric field of dielectric buried layer （EI） and increase breakdown voltage （BV）. The BV and EI of SAC LDMOS increase to 612 V and 600 V/tim from 204 V and 90.7 V/ttm of the conventional silicon-on-insulator, respectively. Moreover, enhancement factors of r/which present the enhanced ability of interface charge on EI are defined and analysed.
