This paper describes the analysis and design of a 0.13μm CMOS tunable receiver front-end that supports 8 TDD LTE bands,covering the 1.8-2.7 GHz frequency band and supporting the 5/10/15/20 MHz bandwidth and QPSK/16QAM/64QAM modulation schemes.The novel zero-IF receiver core consists of a tunable narrowband variable gain low-noise amplifier(LNA),a current commutating passive down-conversion mixer with a 2nd order low pass trans-impedance amplifier,an LO divider,a rough gain step variable gain pre-amplifier,a tunable 4th order Chebyshev channel select active-RC low pass filter with cutoff frequency calibration circuit and a fine gain step variable gain amplifier.The LNA can be tuned by reconfiguring the output parallel LC tank to the responding frequency band,eliminating the fixed center frequency multiple LNA array for a multi-mode receiver. The large various gain range and bandwidth of the analog baseband can also be tuned by digital configuration to satisfy the specification requirement of various bandwidth and modulation schemes.The test chip is implemented in an SMIC 0.13μm 1P8M CMOS process.The full receiver achieves 4.6 dB NF,-14.5 dBm out of band IIP3, 30-94 dB gain range and consumes 54 mA with a 1.2 V power supply.
A new expression is proposed to analyze the linearization effectiveness of derivative superposition(DS) with large and small signal inputs,and different optimization methods of DS are found for different input magnitudes. A power amplifier driver(PAD) with large-signal optimized DS was implemented in 0.13μm technology within a reconfigurable RF transmitter.The PAD is compatible with the GSM band at 900 MHz and the WCDMA band at 1.95 GHz,and it has a gain range of 44 dB with a step of 2 dB.Measurement results show that the overall OIP3 of the transmitter is better than 19 dBm,and the output referred 1-dB compression point is better than 7.5 dBm.
A generally improved recycling folded cascode(IRFC) is analyzed and implemented.Analysis and comparisons among the IRFC,the original recycling folded cascode(RFC) and the conventional folded cascode (FC) are made,and it is shown that with the flexible structure of IRFC,significant enhancement in transconductance, slew rate and noise can be achieved.Prototype amplifiers were fabricated in 0.13μm technology.Measurement shows that IRFC has 3×enhancement in gain-bandwidth and slew rate over conventional FC,and the enhancement is 1.5x when compared with the RFC.
This paper presents an algorithm that can adaptively select the intermediate frequency(IF) and compensate the IQ mismatch according to the power ratio of the adjacent channel interference to the desired signal in a low-IF GSM receiver.The IF can be adaptively selected between 100 and 130 kHz.Test result shows an improvement of phase error from 6.78°to 3.23°.Also a least mean squares(LMS) based IQ mismatch compensation algorithm is applied to improve image rejection ratio(IRR) for the desired signal along with strong adjacent channel interference.The IRR is improved from 29.1 to 44.3 dB in measurement.The design is verified in a low-IF GSM receiver fabricated in SMIC 0.13μm RF CMOS process with a working voltage of 1.2 V.
A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is presented.The transformer not only accomplishes output impedance matching,but also acts as a balun for converting differential signals to single-ended ones.Under a supply voltage of 3.3 V,the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%.The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB,respectively. The die size is 0.91×1.12 mm^2.
This paper presents a 4th-order reconfigurable analog baseband filter for software-defined radios.The design exploits an active-RC low pass filter（LPF） structure with digital assistant,which is flexible for tunability of filter characteristics,such as cut-off frequency,selectivity,type,noise,gain and power.A novel reconfigurable operational amplifier is proposed to realize the optimization of noise and scalability of power dissipation.The chip was fabricated in an SMIC 0.13μm CMOS process.The main filter and frequency calibration circuit occupy 1.8×0.8 mm2 and 0.48×0.25 mm2 areas,respectively.The measurement results indicate that the filter provides Butterworth and Chebyshev responses with a wide frequency tuning range from 280 kHz to 15 MHz and a gain range from 0 to 18 dB.An IIP3 of 29 dBm is achieved under a 1.2 V power supply.The input inferred noise density varies from 41 to 133 nV/（Hz）1/2 according to a given standard,and the power consumptions are 5.46 mW for low band（from 280 kHz to 3 MHz） and 8.74 mW for high band（from 3 to 15 MHz） mode.
This paper describes a low-pass reconfigurable baseband filter for GSM,TD-SCDMA and WCDMA multi-mode transmitters.To comply with 3GPP emission mask and limit TX leakage at the RX band,the out-of -band noise performance is optimized.Due to the distortion caused by the subthreshold leakage current of the switches used in capacitor array,a capacitor bypass technique is proposed to improve the filter’s linearity.An automatic frequency tuning circuit is adopted to compensate the cut-off frequency variation.Simulation results show that the filter achieves an in-band input-referred third-order intercept point(IIP3) of 47 dBm at 1.2-V power supply and the out-of-band noise can meet TX SAW-less requirement for WCDMA & TD-SCDMA.The baseband filter incorporates -40 to 0 dB programmable gain control that is accurately variable in 0.5 dB steps.The filter’s cut-off frequency can be reconfigured for GSM/TD-SCDMAAVCDMA multi-mode transmitter.The implemented baseband filter draws 3.6 mA from a 1.2-V supply in a 0.13μm CMOS process.
A sigma-delta(Σ△) DAC with channel filtering for multi-standard wireless transmitters used in the software-defined-radio(SDR) system is presented.The conversion frequency,transfer function of the digital filter and theΣ△modulator,word-length of the IDAC and cut-off frequency of the analog reconstruction filter can be digitally programmed to satisfy specifications of WCDMA,TD-SCDMA and GSM standards.TheΣ△DAC fabricated in SMIC 0.13-μm CMOS process occupies a die area of 0.72 mm^2,while consuming 5.52/4.82/3.04 mW in WCDMA/TD-SCDMA/GSM mode from a single 1.2-V supply voltage.The measured SFDR is 62.8/60.1/ 75.5 dB for WCDMA/TD-SCDMA/GSM mode,respectively.
