A novel large-signal equivalent circuit model of RF-SOI LDMOS based on Philips MOS Model 20 （MM20） is presented. The weak avalanche effect and the power dissipation caused by self-heating are described. The RF parasitic elements are extracted directly from measured S-parameters with analytical methods. Their final values can be obtained quickly and accurately through the necessary optimization. The model is validated in DC,AC small-signal,and large-signal analyses for an RF-SOI LDMOS of 20-fingers （channel mask length, L = 1μm,finger width, W = 50μm） gate with high resistivity substrate and body-contact. Excellent agreement is achieved between simulated and measured results for DC, S- parameters （10MHz-0.01GHz）, and power characteristics, which shows our model is accurate and reliable. MM20 is improved for RF-SOI LDMOS large-signal applications. This model has been implemented in Verilog-A using the ADS circuit simulator （hpeesofsim）.
A novel scalable model for multi-finger RF MOSFETs modeling is presented.All the parasitic components, including gate resistance,substrate resistance and wiring capacitance,are directly determined from the layout.This model is further verified using a standard 0.13μm RF CMOS process with nMOSFETs of different numbers of gate fingers,with the per gate width fixed at 2.5μm and the gate length at 0.13μm.Excellent agreement between measured and simulated S-parameters from 100 MHz to 20 GHz demonstrate the validity of this model.
