A novel low temperature poly\|Si(LTPS) ultra\|thin channel thin film transistor (UTC\|TFT) technology is proposed. The UTC\|TFT has an ultra\|thin channel region (30nm) and a thick drain/source region (300nm). The ultra\|thin channel region that can result in a lower grain\|boundary trap density in the channel is connected to the heavily\|doped thick drain/source region through a lightly\|doped overlapped region. The overlapped lightly\|doped region provides an effective way for the electric field to spread in the channel near the drain at high drain biases, thereby reducing the electric field there significantly. Simulation results show the UTC\|TFT experiences a 50% reduction in peak lateral electric field compared to that of the conventional TFT. With the low grain\|boundary trap density and low drain electric field, excellent current saturation characteristics and high drain breakdown voltage are achieved in the UTC\|TFT. Moreover, this technology provides the complementary LTPS\|TFTs with more than 2 times increase in on\|current, 3.5 times reduction in off\|current compared to the conventional thick channel LTPS TFTs.
A novel low-cost sub-50nm poly-Si gate patterning technology is proposed and experimentally demonstrated.The technology is resolution-independent,ie.,it does not contain any critical photolithographic steps.The nano-scale masking pattern for gate formation is formed according to the image transfer of an edge-defined spacer.Experimental results reveal that the resultant gate length,about 75 to 85 percent of the thickness,is determined by the thickness of the film to form the spacer.From SEM photograph,the cross-section of the poly-Si gate is seen to be an inverted-trapezoid,which is useful to reduce the gate resistance.
